PXD20RM Datasheet, PDF (979/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 27-9. LINFlexD memory map (LINFlex_0 only) (continued)
Address offset
Register description
0x4C–0x88
0x8C
0x90
0x94
0x98
0x9C
Identifier filter control registers 0–15 (IFCR0–IFCR15)
Global control register (GCR)
UART preset timeout register (UARTPTO)
UART current timeout register (UARTCTO)
DMA Tx enable register (DMATXE)
DMA Rx enable register (DMARXE)
Location
on page 49
on page 50
on page 51
on page 52
on page 53
on page 53
Table 27-10. LINFlexD memory map (LINFlex_1/LINFlex_2/LINFlex_3 only)
Address offset
Register description
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
0x40
0x44
0x48
0x4C
0x50
0x54
0x58
0x5C
LIN control register 1 (LINCR1)
LIN interrupt enable register (LINIER)
LIN status register (LINSR)
LIN error status register (LINESR)
UART mode control register (UARTCR)
UART mode status register (UARTSR)
LIN timeout control status register (LINTCSR)
LIN output compare register (LINOCR)
LIN timeout control register (LINTOCR)
LIN fractional baud rate register (LINFBRR)
LIN integer baud rate register (LINIBRR)
LIN checksum field register (LINCFR)
LIN control register 2 (LINCR2)
Buffer identifier register (BIDR)
Buffer data register least significant (BDRL)
Buffer data register most significant (BDRM)
Identifier filter enable register (IFER)
Identifier filter match index (IFMI)
Identifier filter mode register (IFMR)
Global control register (GCR)
UART preset timeout register (UARTPTO)
UART current timeout register (UARTCTO)
DMA Tx enable register (DMATXE)
DMA Rx enable register (DMARXE)
Location
on page 24
on page 27
on page 29
on page 32
on page 33
on page 36
on page 38
on page 39
on page 40
on page 41
on page 41
on page 42
on page 43
on page 44
on page 45
on page 46
on page 47
on page 47
on page 48
on page 50
on page 51
on page 52
on page 53
on page 53
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
27-23