PXD20RM Datasheet, PDF (1491/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Address: Base + 0x1000 - 0x105C (24 registers)
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R₀
0
0
0
0
0
0
0
0
0
0
0
MAXCNTx[3:0]
W
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 43-19. Interrupt Filter Maximum Counter Registers (IFMC0 - IFMC15)
Table 43-20. IFMC field descriptions
Field
MAXCNTx
[3:0]
Description
Maximum Interrupt Filter Counter setting.
Filter Period = T(IRC)IFCPMAXCNTx + nT(IRC)IFCP
Where n is a synchronisation uncertainty between -1 and 3
MAXCNTx can be 3 to 15. MAXCNT < 3 causes the filter to be bypassed.
T(IRC): Basic Filter Clock Period: 62.5 ns (F = 16 MHz)
43.5.3.17 Interrupt Filter Clock Prescaler Register (IFCPR)
This register is used to configure a clock prescaler which is used to select the clock for all digital filter
counters in the SIUL.
Address: Base + 0x1080
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
R₀
W
Reset ₀
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
IFCP[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 43-20. Interrupt Filter Clock Prescaler Register (IFCPR)
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
43-25