PXD20RM Datasheet, PDF (228/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

A buffered EXTAL signal becomes the internal clock. To improve noise immunity, the oscillator is
powered by the VDDPLL and VSSPLL power supply pins.
8.4.1.7.1 Gain control
A closed loop control system is utilized whereby the amplifier is modulated to keep the output waveform
sinusoidal and to limit the oscillation amplitude. The output peak to peak voltage will be kept above twice
the maximum hysteresis level of the input buffer.
8.4.1.7.2 Clock monitor
The clock monitor circuit is based on an internal RC time delay so that it can operate without any MCU
clocks. If no OSCCLK edges are detected within this RC time delay, the clock monitor indicates failure
which asserts self-clock mode or generates a system reset depending on the state of SCME bit. If the clock
monitor is disabled or the presence of clocks is detected no failure is indicated.The clock monitor function
is enabled/disabled by the CME control bit, described in the MC_CGM chapter.
8.4.2 External crystal oscillator (SXOSC)
8.4.2.1 Features
• External crystal oscillator (SXOSC) digital interface
• Oscillator powerdown control and status
• Oscillator clock available interrupt
• Oscillator bypass mode
• Output clock division factors ranging from 1,2,3....32
8.4.2.2 Functional description
The crystal oscillator circuit includes an internal oscillator driver and an external crystal circuitry. It can
be used as a reference clock to specific modules depending on system needs.
The crystal oscillator is controlled by the OSC_CTL register. The OSCON bit controls the powerdown
while S_OSC bit provides the oscillator clock available status.
After system reset, the oscillator is put to power down state and software has to switch on when required.
Whenever the crystal oscillator is switched on from off state, OSCCNT counter starts and when it reaches
the value EOCV[7:0]*512, oscillator clock is made available to the system. Also an interrupt pending bit
I_OSC of OSC_CTL register is set. An interrupt will be generated if the interrupt mask bit M_OSC is set.
The oscillator circuit can be bypassed by writing OSCBYP bit to OSC_CTL register to ‘1’. This bit can
only be set by the software. System reset is needed to reset this bit. In this bypass mode, the output clock
has the same polarity as external clock applied on EXTAL32 pin and the oscillator status is forced to ‘1’.
The bypass configuration is independent of the powerdown mode of the oscillator.
The table below shows the truth table of different configurations of oscillator.
8-32
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor