PXD20RM Datasheet, PDF (1571/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

47.4 Initialization/Application Information
47.4.1 Initialization Information
When VIU2 block comes out of reset, software should implement the following steps to start this block.
1. Program STATUS_CONFIG register (47.2.3.1/47-5) to set the VIU2 to desired operation mode
— To enable YUV 4:2:2 to 4:4:4 interpolation in ITU decoder, set the MODE444 bit¹
— To enable down-scaler, set the SCALER_EN bit
— To enable B/C adjust, set the BC_EN bit
— To enable RGB565 output mode, set RGB_EN bit and clear MODE32BIT bit. Optionally set
DITHER_ON or ROUND_ON bit to enable dither or round²
— To enable ARGB8888 output mode, set RGB_EN and MODE32BIT bit
— To enable YUV output mode, clear RGB_EN bit
2. Set the FORMAT_CTRL field so that VIU2 outputs data in correct format. Configure the input
video size via the INVSZ register (47.2.3.8/47-11).
3. If want to use RGB output, configure YUV to RGB conversion coefficients (47.2.3.2/47-7,
47.2.3.3/47-8, 47.2.3.4/47-9, 47.2.3.5/47-9) or use the default values after reset.
4. If want to use the down scaling function, program the down scaling factors (47.2.3.11/47-13,
47.2.3.12/47-13), and destination video size after scaling (47.2.3.13/47-14).
5. If want to use the B/C adjust function, program the B/C adjust look-up-table via the LUT_DATA
(47.2.3.15/47-15) and LUT_ADDR (47.2.3.14/47-14) registers.
6. Configure the HPALRM (47.2.3.9/47-12) and ALPHA (47.2.3.10/47-12) registers if necessary.
7. Set the VSYNC_EN and/or FIELD_EN bits in STATUS_CONFIG register to enable vsync or field
interrupt. Meanwhile, disable error interrupt.
8. When software receives vsync interrupt and/or field interrupt, read FIELD_NO bit of
STATUS_CONFIG register³.
9. According to FIELD_NO bit, program the DMA_ADDR register (47.2.3.6/47-10). This is the field
start address in system memory, or frame start address in progressive video input mode.
10. If want to use the de-interlace (weaving) function, program the line start address offset value in the
DMA_INC (47.2.3.7/47-10) register⁴.
11. Clear error status first if necessary.
12. Write DMA_ACT bit of STATUS_CONFIG register to start FIFO and DMA transfer. This
operation actually starts the VIU2 to operate.
1. MODE444 bit shall not be set when the down-scaler is enabled.
2. If DITHER_ON or ROUND_ON are both set, only round will be enabled.
3. Reading the FIELD_NO bit is optional, especially in progressive video input mode.
4. Progressive video input shall be used when down scaling is enabled for better display quality.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
47-23