PXD20RM Datasheet, PDF (42/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

• Chapter 6, Boot Assist Module (BAM), describes the BAM, which contains the MCU boot
program code supporting the different booting modes for this device.
• Chapter 7, CAN Sampler, describes detecting a CAN message while no precise clock is running.
• Chapter 8, Clock Description, describes the various clock sources that are available on the PXD20.
• Chapter 9, Crossbar Switch (XBAR), describes the multi-port AXBS crossbar switch that supports
simultaneous connections between the master ports and slave ports on the PXD20.
• Chapter 10, Deserial Serial Peripheral Interface (DSPI), describes the serial peripheral interface
(SPI) block, which provides a synchronous serial interface for communication between the PXD20
and external devices.
• Chapter 11, Display Control Unit (DCU3), describes the module that displays to a TFT LCD panel.
• Chapter 12, Display Control Unit Lite (DCULite), describes the module that displays to a TFT
LCD panel.
• Chapter 13, DRAM Controller (DRAMC), describes the DRAM controller on the PXD20.
• Chapter 14, DRAMC Priority Manager, describes the submodule of the DRAMC that services
prioritized requests from different buses on the PXD20.
• Chapter 15, e200z4d Core, describes the organization of the e200z4 Power processor cores and an
overview of the programming models as they are implemented on the device.
• Chapter 16, Enhanced Direct Memory Access (eDMA), describes the enhanced DMA controller
implemented on the PXD20.
• Chapter 17, eDMA Channel Mux (DMACHMUX), describes the DMA multiplexer block
implemented on the PXD20.
• Chapter 18, Enhanced Modular IO Subsystem (eMIOS),describes the eMIOS module, which
provides timed I/O channels for communications with off-chip devices.
• Chapter 19, Error Correction Status Module (ECSM), describes the ECSM block, which provides
monitoring and control functions to report memory errors and apply error-correcting code (ECC)
implementations.
• Chapter 20, FlexCAN, describes the CAN module, a communication controller implementing the
CAN protocol according to Bosch Specification version 2.0B and ISO Standard 11898.
• Chapter 21, Flash Memory, describes the flash memory block and the flash memory controller.
• Chapter 22, Graphics Accelerator Gasket (GXG), describes a graphics accelerator (GFX2D) with
a 32-bit IPS-to-AHB bridge to the slave port and a 64-bit AXI-to-AHB bridge to the master port.
• Chapter 23, Graphics Static RAM (GSRAM), describes a block of RAM with an array controller
and dual AHB input ports.
• Chapter 24, IEEE 1149.1 Test Access Port Controller (JTAGC), describes configuration and
operation of the Joint Test Action Group (JTAG) controller implementation. It describes those
items required by the IEEE 1149.1 standard and provides additional information specific to the
device. For internal details and sample applications, see the IEEE 1149.1 document.
• Chapter 25, Inter-Integrated Circuit Bus Controller Module (I2C), describes the I²C module,
including I²C protocol, clock synchronization, and I²C programming model registers.
• Chapter 26, Interrupt Controller (INTC), summarizes the software and hardware interrupts for the
PXD20 device.
PXD20 Microcontroller Reference Manual, Rev. 1
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Freescale Semiconductor
Preliminary—Subject to Change Without Notice