PXD20RM Datasheet, PDF (833/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 21-12. PFAPR field descriptions (continued)
Field
Description
SHSACC[7:4]
Shadow Block Supervisor Access Control. This bit field defines supervisor/user mode access control for each
4 KB sector within the shadow block region of the flash array.
0 Shadow block sector n can be accessed in both user and supervisor mode.
1 Shadow block sector n can be accessed only in supervisor mode. An attempted user mode access is
terminated with an AHB error response. If the requesting bus master is the processor core, the ERROR
response typically generates an instruction abort or data abort exception.
This field is mapped into the shadow block (shadow_block = 0x00FF_C000) with sector base addresses of:
SHSACC[4] = shadow_block + 0x0000
SHSACC[5] = shadow_block + 0x1000
SHSACC[6] = shadow_block + 0x2000
SHSACC[7] = shadow_block + 0x3000
This field is initialized by hardware reset to the value contained in address 0x3E00 of the shadow block of the
flash array. An erased or unprogrammed flash sets this field to 0xFF. The contents of the PFAPR are combined
with the SHSACC field to determine the final flash attributes.
SHDACC[7:4]
Shadow Block Data Access Control. This bit field defines code/data access control for each 4 KByte sector
within the shadow block region of the flash array.
0 Shadow block sector n can only be accessed as data. An attempted instruction fetch access is terminated
with an AHB error response. If the requesting bus master is the processor core, the ERROR response
typically generates an instruction abort or data abort exception.
1 Shadow block sector n can be accessed as either code or data.
This field is mapped into the shadow block using the same definition as the SHSACC field above.
This field is initialized by hardware reset to the value contained in address 0x3E00 of the shadow block of the
flash array. An erased or unprogrammed flash sets this field to 0xFF.
The contents of the PFAPR are combined with the SHDACC field to determine the final flash attributes.
21.3.2.10 PFlash Supervisor Access Control Register (PFSACC)
Offset: FLASH_REGS_BASE + 0x0028
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
W
SACC[30:16]
Reset 0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
SACC[15:0]
W
Reset *
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
* = Initialized by hardware reset
Figure 21-13. PFlash Supervisor Access Control Register (PFSACC)
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
21-21