PXD20RM Datasheet, PDF (450/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

The remaining 4 bits contains make up the protection bits for single bit error correction and detection. It
should be noted that F and V fields are only allowed to change as part of EAV sequences i.e during
transitions from H=0 to H=1.
An entire line of video comprises Active Video + Horizontal Blanking (from the start of the EAV code
until the end of the SAV code) and Vertical Blanking (the space where V = 1).
NOTE
This device supports only 8-bit, non-interlaced, video. The Field (F) value
is ignored.
EAV code
blanking
SAV code
F ⁰ 0 ^X8 1 8 1
F ⁰ 0 ^Y0 0 0 0
8 1 F 0 0X
0 0 F 0 0Y
Active Video Data
Start of
Digital line
Start of
digital Active Line
H Control Signal
Next Line
Figure 11-90. ITU-R BT.656 8 bit parallel data format for 525 video system
Data Bit
FirstWord SecondWord ThirdWord FourthWord
(FF)
(00)
(00)
(XY)
D7(MSB)
1
0
D6
1
0
D5
1
0
D4
1
0
D3
1
0
D2
1
0
D1
1
0
D0
1
0
0
1
0
F
0
V
0
H
0
P3
0
P2
0
P1
0
P0
Figure 11-91. Control Byte Sequence for 8-bit/10-bit video
The bit definitions for the status word XY are shown in Table 11-77.
Table 11-77. Status word definitions
Bit
Definition
F
0 for field 0
1 for field 1
V
1 during vertical blanking period
0 when not in vertical blanking
H
0 at SAV
1 at EAV
11-116
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor