PXD20RM Datasheet, PDF (1599/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Chapter 50
Device Performance Optimization
50.1 Introduction
The PXD20 contains several features that can influence the overall level of performance provided by the
device.
Some of these features may be initialized upon negation of reset either by a software program called the
Boot Assist Module (BAM), by a hardware state machine or by appropriate default register settings.
Although the device exits the reset state into a functional state it does not necessarily have the default
optimum performance settings for any given application.
This chapter provides guidance for users to fully optimize their application to achieve the highest possible
performance from the PXD20. It provides a description of the areas that should be focused on when
optimizing an application for performance by describing the features and recommending settings to be
applied. It focuses on hardware configurations although certain aspects of the application software such as
compiler settings and optimizations will be discussed.
50.2 Features
The PXD20 has the following hardware features that can be configured to impact the overall performance
of the device:
• Branch Prediction
— Branch Target Buffer
— Branch Prediction Control
• Frequency-modulated PLL
• Platform Flash Controller
— Flash access wait state and address pipelining control
— Flash instruction prefetching
— Flash data prefetching
• Crossbar switch
• System Cache
— Instruction Cache
• Memory Management Unit
• DRAM Controller Priority Manager
Further application level features can impact the application performance:
• Hardware Single Precision Floating point
• Signal Processing Extension (SPE-APU)
• Variable Length Encoding (VLE)
• Compiler optimizations
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
50-1