PXD20RM Datasheet, PDF (951/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

the control of the RTOS, the RTOS executes at INTC_CPR priority 0, and while the tasks execute at
different priorities under the control of the RTOS, they also execute at INTC_CPR priority 0.
If a task shares a resource with an ISR and the PCP is being used to manage that shared resource, then the
task’s priority can be elevated in the INTC_CPR while the shared resource is being accessed.
An ISR whose PRIn in INTC priority select registers (INTC_PSR0_3–INTC_PSR236_238) has a value
of 0 will not cause an interrupt request to the processor, even if its peripheral or software settable interrupt
request is asserted. For a peripheral interrupt request, not setting its enable bit or disabling the mask bit
will cause it to remain negated, which consequently also will not cause an interrupt request to the
processor. Since the ISRs are outside the control of the RTOS, this ISR will not run unless called by another
ISR or the interrupt exception handler, perhaps after executing another ISR.
26.7.4 Order of Execution
An ISR with a higher priority can preempt an ISR with a lower priority, regardless of the unique vectors
associated with each of their peripheral or software configurable interrupt requests. However, if multiple
peripheral or software configurable interrupt requests are asserted, more than one has the highest priority,
and that priority is high enough to cause preemption, the INTC selects the one with the lowest unique
vector regardless of the order in time that they asserted. However, the ability to meet deadlines with this
scheduling scheme is no less than if the ISRs execute in the time order that their peripheral or software
configurable interrupt requests asserted.
The example in Table 26-10 shows the order of execution of both ISRs with different priorities and the
same priority
Table 26-10. Order of ISR Execution Example
Step
Step Description
Code Executing at End of Step
PRI in
RTOS
ISR108¹
ISR208
ISR308
ISR408
Interrupt
Exception
Handler
INTC_CPR
at End of
Step
1 RTOS at priority 0 is executing.
X
2 Peripheral interrupt request 100 at
X
priority 1 asserts. Interrupt taken.
3 Peripheral interrupt request 400 at
priority 4 is asserts. Interrupt taken.
4 Peripheral interrupt request 300 at
priority 3 is asserts.
5 Peripheral interrupt request 200 at
priority 3 is asserts.
6 ISR408 completes. Interrupt
exception handler writes to
INTC_EOIR.
7 Interrupt taken. ISR208 starts to
X
execute, even though peripheral
interrupt request 300 asserted first.
0
1
X
4
X
4
X
4
X
1
3
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
26-29