PXD20RM Datasheet, PDF (318/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

PASC
0b01
Table 10-21. After SCK Delay Computation Example
Prescaler
Value
3
ASC
0b0100
Scaler
Value
32
f_SYS
100 MHz
After SCK Delay
0.96 s
10.9.4.4 Delay after Transfer (t_DT)
The delay after transfer is the length of time between negation of the CSx signal for a frame and the
assertion of the CSx signal for the next frame. The PDT and DT fields in the DSPIx_CTARn registers
select the delay after transfer.
Refer to Figure 10-14 for an illustration of the delay after transfer.
The following formula expresses the PDT/DT/delay after transfer relationship:
t_DT =
1
f_SYS

PDT
 DT
Table 10-22 shows an example of the computed delay after transfer.
Table 10-22. Delay after Transfer Computation Example
PDT
0b01
Prescaler
Value
3
DT
0b1110
Scaler
Value
32768
f_SYS
Delay after Transfer
100 MHz
0.98 ms
When in non-continuous clock mode the t_DT delay is configurable as outlined in the DSPI_CTARx
registers. When in continuous clock mode and TSB is not enabled the delay is fixed at 1 SCK period. When
in TSB and continuous mode the delay is programmed as outlined in the DSPI_CTARx registers but in the
event that the delay does not coincide with an SCK period in duration the delay is extended to the next
SCK active edge. Table 10-23 shows an example of how to compute the Delay after Transfer with the clock
period of SCK defined as T_SCK. The values calculated assume 1 TSCK period = 4 ipg_clk.
10-32
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor