PXD20RM Datasheet, PDF (603/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 14-1. Detailed Signal Description
Signal
ipmx1_req_ack
ipmx2_req_ack
ipmx3_req_ack
ipmx4_req_ack
ipmx0_prio_in[0:3]
ipmx0_prio[0:3]
ipmx1_prio[0:3]
ipmx2_prio[0:3]
ipmx3_prio[0:3]
ipmx4_prio[0:3]
ips_module_en
ips_addr[0:8]
ips_rwb
ips_byte_en[0:3]
ips_wdata[0:31]
ips_rdata[0:31]
I/O
Description
I DRAMC request acknowledge for bus 1
I DRAMC request acknowledge for bus 2
I DRAMC request acknowledge for bus 3
I DRAMC request acknowledge for bus 4
I Incoming priority signal for DCU (bus 0)
O Outgoing priority signal to DRAMC for bus 0
O Outgoing priority signal to DRAMC for bus 1
O Outgoing priority signal to DRAMC for bus 2
O Outgoing priority signal to DRAMC for bus 3
O Outgoing priority signal to DRAMC for bus 4
I Slave bus module enable
I Slave bus address
I Slave bus read/write signal
I Slave bus byte enables
I Slave bus write data bus
O Slave bus read data bus
14.4 Memory map and register definition
14.4.1 Memory map
Table 14-2. Priority manager memory map
Offset or
Address
Register
0x80
0x84
0x88
0x8C
0x90
0x94
0x98
0x9C
0xA0
0xA4
prioman_config1 (CFG1)
prioman_config2 (CFG2)
hiprio_config (HPCFG)
LUT 0 main upper (MLUTU0)
LUT 1 main upper (MLUTU1)
LUT 2 main upper (MLUTU2)
LUT 3 main upper (MLUTU3)
LUT 4 main upper (MLUTU4)
LUT 0 main lower (MLUTL0)
LUT 1 main lower (MLUTL1)
Access Reset value
R/W 0x0007_7777
R/W 0x0000_0011
R/W
0x0
R/W 0x01111_1222
R/W 0x01111_1222
R/W 0x01111_1222
R/W 0x01111_1222
R/W 0x01111_1222
R/W 0x2334_567A
R/W 0x2334_567A
Location
on page 14-5
on page 14-5
on page 14-7
on page 14-8
on page 14-8
on page 14-8
on page 14-8
on page 14-8
on page 14-9
on page 14-9
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
14-3