PXD20RM Datasheet, PDF (713/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

address: eMIOS0 base address +0x04
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R₀
0
0
0
0
0
0
0 F23 F22 F21 F20 F19 F18 F17 F16
W
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R _{F15 F14 F13 F12 F11 F10 F9}
F8
0
0
0
0
0
0
0
0
W
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 18-5. eMIOS200 Global FLAG Register (GFR)
F[n] — Channel [n] Flag bit
Channels that occupy a pair of slots are referred to by their lower slot number (LSB=0 standard), therefore
the bits corresponding to their higher slot number always read 0.
18.6.2.3 eMIOS200 Output Update Disable (OUDR)
The two modules on this device, EMIOS0 and EMIOS1, have the same structure for this register as shown
in Figure 18-6.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
18-11