PXD20RM Datasheet, PDF (271/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

9.4.1.1 Arbitration During Undefined Length Bursts
Arbitration points during an undefined length burst are defined by the current master’s MGPCR AULB
field setting. When a defined length is imposed on the burst via the AULB bits the undefined length burst
will be treated as a single or series of single back to back fixed length burst accesses.
Example: A master runs an undefined length burst and the AULB bits in the MGPCR indicate arbitration
will occur after the fourth beat of the burst. The master runs two sequential beats and then starts what will
be an 12 beat undefined length burst access to a new address within the same slave port region as the
previous access. The XBAR will not allow an arbitration point until the fourth overall access (second beat
of the second burst). At that point all remaining accesses will be open for arbitration until the master loses
control of the slave port.
Assume the master loses control of the slave port after the fifth beat of the second burst. Once the master
regains control of the slave port no arbitration point will be available until after the master has run four
more beats of its burst. After the fourth beat of the (now continued) burst (ninth beat of the second burst
from the master’s perspective) is taken all beats of the burst will once again be open for arbitration until
the master loses control of the slave port.
Assume the master again loses control of the slave port on the fifth beat of the third (now continued) burst
(10th beat of the second burst from the master’s perspective). Once the master regains control of the slave
port it will be allowed to complete its final two beats of its burst without facing arbitration.
Note that fixed length burst accesses are not affected by the AULB bits. All fixed length burst accesses
lock out arbitration until the last beat of the fixed length burst.
9.4.1.2 Fixed Priority Operation
When operating in fixed-priority mode, each master is assigned a unique priority level in the MPR (Master
Priority Register). If two masters both request access to a slave port the master with the highest priority in
the selected priority register will gain control over the slave port.
Any time a master makes a request to a slave port the slave port checks to see if the new requesting master’s
priority level is higher than that of the master that currently has control over the slave port (unless the slave
port is in a parked state). The slave port does an arbitration check at every clock edge to ensure that the
proper master (if any) has control of the slave port.
If the new requesting master’s priority level is higher than that of the master that currently has control of
the slave port the new requesting master will be granted control over the slave port at the next clock edge.
The exception to this rule is if the master that currently has control over the slave port is running a fixed
length burst transfer or a locked transfer. In this case the new requesting master will have to wait until the
end of the burst transfer or locked transfer before it will be granted control of the slave port. If the master
is running an undefined length burst transfer the new requesting master must wait until an arbitration point
for the undefined length burst transfer before it will be granted control of the slave port. Arbitration points
for an undefined length burst are defined in the MGPCR for each master.
If the new requesting master’s priority level is lower than that of the master that currently has control of
the slave port the new requesting master will be forced to wait until the master that currently has control
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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