PXD20RM Datasheet, PDF (750/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 19-1. ECSM memory map (continued)
Address offset
Register
0x48–0x49
0x4A
0x4C–0x4F
0x50
0x54–0x55
0x56
0x57
0x58–5B
0x5C
0x60
0x64
0x65
0x66
0x67
0x68–0x6B
0x6C
Reserved
ECC Error Generation Register (EEGR)
Reserved
Flash ECC Address Register (FEAR)
Reserved
Flash ECC Master Number Register (FEMR)
Flash ECC Attributes (FEAT)
Reserved
Flash ECC Data Register (FEDR)
RAM ECC Address Register (REAR)
Reserved
RAM ECC Syndrome Register (RESR)
RAM ECC Master Register (REMR)
RAM ECC Attributes (REAT)
Reserved
RAM ECC Data Register (REDR)
Location
on page 19-7
on page 19-10
on page 19-10
on page 19-11
on page 19-12
on page 19-13
on page 19-13
on page 19-15
on page 19-16
on page 19-17
19.4.2 Register description
Attempted accesses to reserved addresses result in an error termination, while attempted writes to
read-only registers are ignored and do not terminate with an error. Unless noted otherwise, writes to the
programming model must match the size of the register, e.g., an n-bit register only supports n-bit writes,
etc. Attempted writes of a different size than the register width produce an error termination of the bus
cycle and no change to the targeted register.
19.4.2.1 Miscellaneous User-Defined Control Register (MUDCR)
The MUDCR provides a program-visible register for user-defined control functions. It typically is used as
configuration control for miscellaneous device-level modules. The contents of this register is simply
output from ECSM to other modules where the user-defined control functions are implemented. See
Figure 19-1 and Table 19-2 for the Miscellaneous User-Defined Control Register definition.
19-2
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor