PXD20RM Datasheet, PDF (822/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 21-3. MCR Field Descriptions (continued)
Field
Description
ESUS
Erase Suspend. ESUS is used to indicate that the flash module is in erase suspend or in the process of entering a
suspend state. The module is in erase suspend when ESUS = 1 and DONE = 1. ESUS can be set high only when
ERS and EHV are high and PGM is low. A 0 to 1 transition of ESUS starts the sequence which sets DONE and
places the flash in erase suspend.
ESUS can be cleared only when DONE and EHV are high and PGM is low. A 1 to 0 transition of ESUS with EHV = 1
starts the sequence which clears DONE and returns the module to erase. The flash module cannot exit erase
suspend and clear DONE while EHV is low. ESUS is cleared on reset.
0 Erase sequence is not suspended.
1 Erase sequence is suspended.
EHV
Enable High Voltage. The EHV bit enables the flash module for a high voltage program/erase operation. EHV is
cleared on reset. EHV must be set after an interlock write to start a program/erase sequence. EHV may be set,
initiating a program/erase, after an interlock under one of the following conditions:
• Erase (ERS = 1, ESUS = 0).
• Program (ERS = 0, ESUS = 0, PGM = 1, PSUS = 0).
• Erase-suspended program (ERS = 1, ESUS = 1, PGM = 1, PSUS = 0).
If a program operation is to be initiated while an erase is suspended the user must clear EHV while in erase suspend
before setting PGM.
In normal operation, a 1 to 0 transition of EHV with DONE high, PSUS and ESUS low terminates the current
program/erase high voltage operation.
When an operation is aborted, there is a 1 to 0 transition of EHV with DONE low and the suspend bit for the current
program/erase sequence low. An abort causes the value of PEG to be cleared, indicating a failed program/erase;
address locations being operated on by the aborted operation contain indeterminate data after an abort.
A suspended operation cannot be aborted. EHV may be written during suspend. EHV must be high for the flash
module to exit suspend. EHV may not be written after a suspend bit is set high and before DONE transitions high.
EHV may not be set low after the current suspend bit is set low and before DONE transitions low.
0 Flash is not enabled to perform a high voltage operation.
1 Flash is enabled to perform a high voltage operation.
Note: Aborting a high voltage operation leaves FC addresses in an indeterminate data state. This may be
recovered by executing an erase on the affected blocks.
21.3.2.1.1 MCR Simultaneous Register Writes
A number of MCR bits are protected against write when another bit, or set of bits, is in a specific state.
These write locks are covered on a bit by bit basis in the preceding section. The write locks detailed in the
previous section do not consider the effects of trying to write two or more bits simultaneously. The effects
of writing bits simultaneously which put the module in an illegal state are detailed here.
The flash module does not allow the user to write bits simultaneously which put the device into an illegal
state. This is implemented through a priority mechanism among the bits. The bit changing priorities are
detailed in Table 21-4.
Table 21-4. MCR Bit Set/Clear Priority Levels
Priority Level
1
2
3
4
MCR Bit(s)
ERS
PGM
EHV
ESUS, PSUS
21-10
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor