PXD20RM Datasheet, PDF (1250/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

The conditions given above ensure that there is no SFM Command currently executed, all the data read
into the RX Buffer from the serial flash have been fetched by the application. It is also ensured that no
current AHB access, no active DMA nor any enabled interrupt is pending
Note that it is not visible to the application whether the module has already negated the ipg_enable_clk.
While the clocks are shut off, the QuadSPI memory-mapped logic is not accessible. Certain read or write
operations have a different effect when the QuadSPI is in the Stop Mode. In the Stop Mode not all of the
status and flag bits of the QuadSPI module are updated and writing to them will have no effect. Interrupt
and DMA request signals cannot be cleared while in the Stop Mode.
Note that there is a time where it is illegal to issue a new SFM Command. This time starts, due to the
internal processing pipeline, 2 clock cycles prior to raising the request to go into Stop Mode. This time
ends with leaving the Stop Mode.
35.5.4.2 Module Disable Mode
Module Disable Mode is a block-specific mode that the QuadSPI can enter to save power. There are two
possibilities to request entering the Module Disable Mode:
• Host software can initiate the Module Disable Mode by writing a ‘1’ to the MDIS bit in the
QSPI_MCR.
• The Module Disable Mode can also be initiated by hardware. A power management block can
initiate Module Disable Mode by asserting the ipg_doze signal while the DOZE bit in the
QSPI_MCR is asserted.
When a request is encountered to enter the Module Disable Mode the QuadSPI negates ipg_enable_clk
when it is ready to enter the Module Disable Mode.
The condition to enter the Module Disable Mode is reached when:
• QSPI_SFMSR[BUSY] = 0 and
• QSPI_SFMSR[AHBTRN] = 0 and
• QSPI_RBSR[RDBFL] = 0
• QSPI_SFMSR[RXDMA] = 0
• None of the flags in the QSPI_SFMFR register enabled as interrupts is set
The conditions given above ensure that there is no SFM Command currently executed, all the data read
into the RX Buffer from the serial flash have been fetched by the application. It is also ensured that no
current AHB access, no active DMA nor any enabled interrupt is pending
Note that it is not visible to the application whether the module has already negated the ipg_enable_clk.
If implemented, the ipg_enable_clk signal can stop the clock to the non-memory mapped logic. When
ipg_enable_clk is negated and the ipg_clk is stopped the QuadSPI is in a dormant state, but the memory
mapped registers are still accessible. Certain read or write operations have a different effect when the
QuadSPI is in the Module Disable Mode. In the Module Disable Mode not all of the status and flag bits of
the QuadSPI module are updated and writing to them will have no effect. Interrupt and DMA request
signals cannot be cleared while in the Module Disable Mode.
35-40
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor