PXD20RM Datasheet, PDF (245/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

8.6.4.1 Control Status Register (CMU_CSR)
Address offset: 0x00
Reset value: 0x00000006
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
reserved
SFM
reserved
r
rs
r
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
CLKSEL1
reserved
RCDIV
CME_
A
r
rw
r
Table 8-36. Control Status Register (CMU_CSR)
rw
rw
Table 8-37. Control Status Register (CMU_CSR) field descriptions
Field
Description
8
SFM
Start frequency measure
The software can only set this bit to start a clock frequency measure. It is reset by
hardware when the measure is ready in the CMU_FDR register.
0: Frequency measurement is completed or not yet started.
1: Frequency measurement is not completed.
22-23
CLKSEL1
RC Oscillator(s) selection bit
CLKSEL1 selects the clock to be measured by the frequency meter.
00: CK_FIRC is selected.
01: CK_SIRC is selected.
10: CK_SXOSC crystal Oscillator clock is selected.
11: CK_FIRC is selected.
29-30
RCDIV[1:0
]
RC clock division factor
These bits specify the
the factor 2^RCDIV. This
RC clock division factor. The output clock is CK_IRC_fast divided by
output clock is used to compare with CK_FXOSC for crystal clock
monitor feature.The clock division coding is as follows.
00: Clock divided by 1 (No division)
01: Clock divided by 2
10: Clock divided by 4
11: Clock divided by 8
31
CME_A
FMPLL0 clock monitor enable
0: FMPLL0 monitor is disabled.
1: FMPLL0 monitor is enabled.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
8-49