PXD20RM Datasheet, PDF (520/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Field
HLB
Table 12-48. Global Protection Register Field Descriptions
Description
Hard Lock Bit. This bit cannot be cleared once it is set by software. It can only be cleared by a
system reset.
1’b1:All SLB’s are write protected & cannot be modified
1’b0:All SLB’s are accessible & can be modified
12.3.4.45 Soft Lock Bit Register L0
Figure 12-55 represents the Soft Lock Bit Register for Layer0. This is used to protect the 7 control
descriptor layer registers for Layer0.
Offset: 0x304
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R0 0 0 0
0000
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1
Figure 12-55. Soft Lock Register L0
Table 12-49. Soft Lock Register L0 field descriptions
Field
WEN_L0_1
WEN_L0_2
WEN_L0_3
WEN_L0_4
Description
Write Enable for Soft Lock Bit SLB_L0_1
1’b1: Value is written to SLB
1’b0: SLB is not modified
Write Enable for Soft Lock Bit SLB_L0_2
1’b1: Value is written to SLB
1’b0: SLB is not modified
Write Enable for Soft Lock Bit SLB_L0_3
1’b1: Value is written to SLB
1’b0: SLB is not modified
Write Enable for Soft Lock Bit SLB_L0_4
1’b1: Value is written to SLB
1’b0: SLB is not modified
12-58
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor