PXD20RM Datasheet, PDF (927/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

26.5.2.1 INTC Module Configuration Register (INTC_MCR)
The module configuration register is used to configure options of the INTC.
Offset: 0x0000
0
1
R₀
0
W
Reset ₀
0
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
0
Access: User read/write
8
9
10
11 12 13 14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
R₀
W
Reset ₀
Field
VTES
HVEN
17
18
19 20 21 22
23
24 25
26
27 28 29 30
31
0
0
0
0
0
0
0
0
0 VTES 0
0
0
0 HVEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-2. INTC Module Configuration Register (INTC_MCR)
Table 26-2. INTC_MCR Field Descriptions
Description
Vector table entry size. Controls the number of ‘0’s to the right of INTVEC in Section 26.5.2.3, INTC
Interrupt Acknowledge Register (INTC_IACKR)). If the contents of INTC_IACKR are used as an
address of an entry in a vectortable as in software vector mode, then the number of rightmost ‘0’s
will determine the size of each vector table entry. VTES impacts software vector mode operation but
also affects INTC_IACKR[INTVEC] position in both hardware vector mode and software vector
mode.
0 4 bytes.
1 8 bytes.
Hardware vector enable. Controls whether the INTC is in hardware vector mode or software vector
mode. Refer to Section 26.4, Modes of operation, for the details of the handshaking with the
processor in each mode.
0 Software vector mode.
1 Hardware vector mode.
26.5.2.2 INTC Current Priority Register for Processor (INTC_CPR)
Offset: 0x0008
Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R_{0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0}
PRI
W
Reset _{0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1}
Figure 26-3. INTC Current Priority Register (INTC_CPR)
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
26-5