PXD20RM Datasheet, PDF (1376/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

If 4 channels are selected, division by 4;
39.7.8 I2S Interface
It is possible to select either PWM or I2S options for the output of the mixed sample data. The output
option chosen does not affect the hardware or process for creating the mixed sound. This section describes
the I2S block.
39.7.8.1 Features
The I2S interface has the following features:
• Synchronous Master mode support only
• Output sample support
— 16-bit per channel
— 32-bit per channel
— 16-bit encapsulated in 32-bit
• Same data can be repeated on the both left and right channels
• Supported protocol modes
— Philips (stereo)
— I2S MSB Justify (stereo)
— I2S LSB Justify
— PCM (mono)
• For PCM mode
— Only 16-bit input audio data is supported
— Output data supported format is 16-bit or 16-bit extended 32-bit
— Programmable frame sync width of 1 to up to 13-bit clocks i.e. support for long and short frame
synchro
• For extended bit formats, following data repetition options are supported
— Append sign bits (For LSB justified modes)
— Repeat MSBits (for MSB justified modes)
— Stuff 0's (all extended modes)
— Stuff 1's (all extended modes)
• Additional clock output port support with programmable frequency of
— 256 × Frame clock
— 512 × Frame clock
• Programmable polarity for clock, data and frame synchronisation signals
• 16-bit pre-scaler to support different SCK clock frequency
• 8 word deep (32-bit wide) fifo for buffering audio data output data
• Programmable FIFO thresholds to start I2S data transfer
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PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor