PXD20RM Datasheet, PDF (826/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

The SLL register is shown in Figure 21-6 and Table 21-7.
Offset: FLASH_REGS_BASE + 0x000C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R SLE 0
0
0
0
0
0
0
0
0
0 _SS 0
0
W
LOCK
SM
LOCK
Reset 0
0
0
0
0
0
0
0
0
0
0 1* 0
0
1*
1*
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
0
0
0
0
W
SLLOCK
Reset 0
0
0
0
0
0 1* 1* 1* 1* 1* 1* 1* 1* 1*
1*
Figure 21-6. Secondary Low/Mid Address Block Locking Register (SLL)
Table 21-7. SLL Field Descriptions
Field
SLE
SSLOCK
SMLOCK[1:0]
SLLOCK[9:0]
Description
Secondary Low/Mid Address Lock Enable. This bit is used to enable the Lock registers (SSLOCK,
SMLOCK, and SLLOCK) to be set or cleared by register writes. This bit is a status bit only, and may not
be written or cleared, and the reset value is 0. The method to set this bit is to provide a password, and
if the password matches, the SLE bit is set to reflect the status of enabled, and is enabled until a reset
operation occurs. For SLE, the password 0xC3C3_3333 must be written to the SLL register
0 Secondary Low/Mid Address Locks are disabled, and cannot be modified.
1 Secondary Low/Mid Address Locks are enabled to be written.
Secondary Shadow Lock. This bit is an alternative method that may be used to lock the shadow block
from programs and erases. SSLOCK has the same description as SLOCK. SSLOCK is not writable
unless SLE is high.
Secondary Mid Address Block Lock. This bit is an alternative method that may be used to lock the Mid
Address Space blocks from programs and erases. SMLOCK has the same description as MLOCK.
SMLOCK is not writable unless SLE is high.
Secondary Low Address Block Lock. This bit is an alternative method that may be used to lock the Low
Address Space blocks from programs and erases. SLLOCK has the same description as LLOCK.
SLLOCK is not writable unless SLE is high.
21.3.2.5 Low/Mid Address Space Block Select Register (LMS)
The Low/Mid Address Space Block Select Register (LMS) provides a means to select blocks to be
operated on during erase.
The LMS register is shown in Figure 21-7 and Table 21-8.
21-14
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor