PXD20RM Datasheet, PDF (247/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

8.6.4.4 Low Frequency Reference Register FMPLL0 (CMU_LFREFR)
Address offset: 0x0C
Reset value: 0x00000000
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
reserved
r
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
LFREF[11:0]
r
rw
Table 8-42. Low Frequency Reference Register FMPLL0
Table 8-43. Low Frequency Reference Register FMPLL0 field descriptions
Field
20-31
LFREF
Description
Low Frequency reference value
These bits determine the low reference value for the FMPLL0. The reference value is
given by: (LFREF[11:0]/16) * (FRC_fast/4).
8.6.4.5 Interrupt Status Register (CMU_ISR)
Address offset: 0x10
Reset value: 0x00000000
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
reserved
r
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
FHHI FLLI OLRI
r
Table 8-44. Interrupt Status Register (CMU_ISR)
rc
rc
rc
Table 8-45. Interrupt Status Register (CMU_ISR) field descriptions
Field
29
FHHI
Description
FMPLL0 Clock frequency higher than high reference interrupt
This bit is set by hardware when CK_FMPLL frequency becomes higher than HFREF
value and CK_FMPLL is ‘ON’ as signalled by the MC_ME. It can be cleared by software
by writing ‘1’.
0: No FHH event.
1: FHH event is pending.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
8-51