PXD20RM Datasheet, PDF (277/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

The muxes are a series of 8 to 1 muxes that take in all the address, control and write data information from
each of the master ports and then pass the correct master’s signals to the slave port. The state machine
controls all the muxes.
The state machine is where the main slave port arbitration occurs, it decides which master is in control of
the slave port and which master will be in control of the slave port in the next bus cycle.
A block diagram of a slave port can be seen in Figure 9-7.
Registers
Read_sel
Write_sel ^ampr_sel
Wdata
Control_bits
Xfr_wait
Xfr_error
Rdata
State Machine
Master_requests[7:0] Control_bits
m[7:0]_high_priority
halt_request
Slv_hready
Slv_hresp
slave_halted
Master_sel[7:0]
Current_master[7:0]
Master_hready[7:0]
Force_idle
Force_nseq
Master_hresp[7:0]
Muxes
Force_nseq
Force_idle
Master_addr[7:0] Master_sel[7:0]
Master_cntrl[7:0] Slv_addr_signals
Master_wdata[7:0] Slv_cntrl_signals
Slv_wdata
Figure 9-7. XBAR Slave Port Block Diagram
9.4.4.2 Slave Port Muxes
The block diagram (Figure 9-7) shows only one block for all the muxes. In reality that block instantiates
many 8 to 1 muxes, one for each master-to-slave signal in fact. All the muxes are designed in an AND -
OR fashion, so that if no master is selected the output of the muxes will be zero. (This is an important
feature for low power park mode.)
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
9-19