PXD20RM Datasheet, PDF (1494/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Int
Vectors
IRQ_23_16
IRQ_15_08¹
IRQ_07_00
OR
OR
OR
Interrupt enable
IRE[23:0]¹
Glitch filter Prescaler
IFCP[3:0]
Glitch filter Counter_n
MAXCOUNT[x]
IRQ Glitch Filter enable
IFE[23:0]¹
EIF[23:16]¹
EIF[15:8]¹
Edge detection
Glitch filter
Pads
EIF[7:0]
Interrupt Edge Enable
Rising
IREE[23:0]¹
Falling
IFEE[23:0]¹
Figure 43-22. External interrupt pad diagram
1 _{Bit count is [0:15] in the 176-pin package, [0:18] in the 208-pin package, and [0:23] in the 416-pin package.}
43.6.4.1 External interrupt management
Each interrupt can be enabled or disabled independently. This can be performed using the Interrupt
Request Enable Register (IRER - Section 43.5.3.4, Interrupt Request Enable Register (IRER)). A pad
defined as an external interrupt can be configured to recognize interrupts with an active rising edge, an
active falling edge or both edges being active. A setting of having both edge events disabled is reserved
and should not be configured. External interrupts require that the associated input buffer for the pad is
enabled (PCR[IBE]=1).
The active EIRQ edge is controlled through the configuration of the registers IREER and IFEER.
Each external interrupt supports an individual flag which is held in the Flag register (ISR -
Section 43.5.3.3, Interrupt Status Flag Register (ISR)). This register is a clear-by-write-1 register type,
preventing inadvertent overwriting of other flags in the same register.
43.7 Pin muxing
For pin muxing, please refer to Chapter 3, Signal Description, of this document.
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PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor