PXD20RM Datasheet, PDF (1604/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

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SPR - 1011; Read/Write; Reset - 0x0
Figure 50-2. L1 Cache Control and Status Register 1 (L1CSR1)
Table 50-2. L1CSR1 field descriptions
Field
ICECE
ICEI
ICEDT
ICUL
ICLO
ICLFC
ICLOA
ICEA
ICABT
ICINV
ICE
Description
Instruction Cache Error Checking Enable
Instruction Cache Error Injection Enable
Instruction Cache Error Detection Type
Instruction Cache Unable to Lock
Instruction Cache Lock Overflow
Instruction Cache Lock Bits Flash Clear
Instruction Cache Lock Overflow Allocate
Instruction Cache Error Action
Instruction Cache Operation Aborted
Indicates a Cache Invalidate or a Cache Lock Bits Flash Clear operation was aborted prior to
completion. This bit is set by hardware on an aborted condition, and will remain set until cleared by
software writing 0 to this bit location.
Instruction Cache Invalidate
0: No cache invalidate
1: Cache invalidation operation
When written to a ‘1’, a cache invalidation operation is initiated by hardware. Once complete, this bit is
reset to ‘0’. Writing a ‘1’ while an invalidation operation is in progress will result in an undefined
operation. Writing a ‘0’ to this bit while an invalidation operation is in progress will be ignored. Cache
invalidation operations require approximately 36 cycles to complete. Invalidation occurs regardless of
the enable (ICE) value.
During cache invalidations, the parity check bits are written with a value dependent on the ICEDT
selection. ICEDT should be written with the desired value for subsequent cache operation when ICINV
is set to ‘1’ for proper operation of the cache.
Instruction Cache Enable
0: Cache is disabled
1: Cache is enabled
When disabled, cache lookups are not performed for instruction accesses.
Other L1CSR0 cache control operations are still available.
Note that configuration of the cache has to be performed in conjunction with configuration of the Memory
Management unit. Refer to section Section 50.3.6, Memory management unit (MMU).
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PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor