PXD20RM Datasheet, PDF (947/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

INTVEC field retains that value until the next time the interrupt request to the processor is asserted. The
rest of handshaking process is described in Section 26.4.1.1, Software vector mode.
26.6.3.1.2 End of Interrupt Exception Handler
Before the interrupt exception handling completes, INTC end-of-interrupt register (INTC_EOIR) must be
written.When written, the associated LIFO is popped so the preempted priority is restored into PRI of the
INTC_CPR. Before it is written, the peripheral or software configurable flag bit must be cleared so that
the peripheral or software configurable interrupt request is negated.
NOTE
To ensure proper operation across all eSys MCUs, execute an MBAR or
MSYNC instruction between the access to clear the flag bit and the write to
the INTC_EOIR.
When returning from the preemption, the INTC does not search for the peripheral or software settable
interrupt request whose ISR was preempted. Depending on how much the ISR progressed, that interrupt
request may no longer even be asserted. When PRI in INTC_CPR is lowered to the priority of the
preempted ISR, the interrupt request for the preempted ISR or any other asserted peripheral or software
settable interrupt request at or below that priority will not cause a preemption. Instead, after the restoration
of the preempted context, the processor will return to the instruction address that it was to next execute
before it was preempted. This next instruction is part of the preempted ISR or the interrupt exception
handler’s prolog or epilog.
Clock
Interrupt request to processor
Hardware vector enable
Interrupt vector
0
Interrupt acknowledge
Read INTC_IACKR
Write INTC_EOIR
INTVEC in INTC_IACKR
0
108
PRI in INTC_CPR
0
1
Peripheral interrupt request 100
Figure 26-10. Software Vector Mode Handshaking Timing Diagram
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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