PXD20RM Datasheet, PDF (224/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

• Section 8.3.3.1.5, System Clock Divider Configuration Registers (CGM_SC_DC0…3)
• Section 8.3.3.1.7, Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC)
• Section 8.3.3.1.9, Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC)
• Section 8.3.3.1.11, Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC)
• Section 8.3.3.1.13, Auxiliary Clock 3 Divider Configuration Register (CGM_AC3_DC)
• Section 8.3.3.1.15, Auxiliary Clock 4 Divider Configuration Register (CGM_AC4_DC)
The reset value of all counters is ‘1’. If a divider has its DE bit in the respective configuration register set
to ‘0’ (the divider is disabled), any value in its DIVn field is ignored.
8.3.4.3 DRAM Controller Clock
For correct operation, the DRAM controller requires two clocks: the system clock and 2x system clock.
Since the only clock source available on the device that can provide this is the FMPLL0, the DRAM
Controller can only operate when FMPLL0 is selected as the system clock. This is not a limitation because
in practice FMPLL0 is the only clock that can provide operating frequencies high enough for the DRAM
controller.
8.3.4.4 Output Clock Multiplexing
The MC_CGM contains a multiplexing function for a number of clock sources which can then be used as
output clock sources. The selection is done via the CGM_OCDS_SC register.
8.3.4.5 Output Clock Division Selection
16 MHz int. RC osc.
0
4-16 MHz ext. xtal osc.
1
primary PLL/2
2
secondary PLL
3
128 kHz int. RC osc.
4
32 kHz ext. xtal osc.
5
reserved
6
RTC clock
7
system clock
8
CGM_OC_EN Register
3
2 ^{‘0’}
1
0
PA[0]
CGM_OCDS_SC.SELCTL
Register
CGM_OCDS_SC.SELDIV
Register
Figure 8-25. MC_CGM Output Clock Multiplexer and PA[0] Generation
The MC_CGM provides the following output signals for the output clock generation:
• PA[0] (see Figure 8-25). This signal is generated by using one of the 3-stage ripple counter outputs
or the selected signal without division. The non-divided signal is not guaranteed to be 50% duty
cycle by the MC_CGM.
8-28
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor