PXD20RM Datasheet, PDF (985/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Field
LINS
RMB
RBSY
RPS
Table 27-16. LINSR field descriptions
Description
LIN state
LIN mode states description
0000: Sleep mode
LINFlexD is in Sleep mode to save power consumption.
0001: Initialization mode
LINFlexD is in Initialization mode.
0010: Idle
This state is entered on several events:
• SLEEP bit and INIT in LINCR1 register have been cleared by software,
• A falling edge has been received on RX pin and AWUM bit is set,
• The previous frame reception or transmission has been completed or aborted.
0011: Break
In Slave mode, a falling edge followed by a dominant state has been detected. Receiving Break.
Note: In Slave mode, in case of error new LIN state can be either Idle or Break depending on last bit
state. If last bit is dominant new LIN state is Break, otherwise Idle.
In Master mode, Break transmission ongoing.
0100: Break Delimiter
In Slave mode, a valid Break has been detected. Refer to LINCR1 register for break length
configuration (10-bit or 11-bit). Waiting for a rising edge.
In Master mode, Break transmission has been completed. Break Delimiter transmission is ongoing.
0101: Synch Field
In Slave mode, a valid Break Delimiter has been detected (recessive state for at least one bit time).
Receiving Synch Field.
In Master mode, Synch Field transmission is ongoing.
0110: Identifier Field
In Slave mode, a valid Synch Field has been received. Receiving ID Field.
In Master mode, identifier transmission is ongoing.
0111: Header reception/transmission completed
In Slave mode, a valid header has been received and identifier field is available in the BIDR register.
In Master mode, header transmission is completed.
1000: Data reception/transmission
Response reception/transmission is ongoing.
1001: Checksum
Data reception/transmission completed. Checksum reception/transmission ongoing.
In UART mode, only the following states are flagged by the LIN state bits:
• Init
• Sleep
• Idle
• Data transmission/reception
Release Message Buffer
0: Buffer is free
1: Buffer ready to be read by software. This bit must be cleared by software after reading data received
in the buffer.
This bit is cleared by hardware in Initialization mode.
Receiver Busy Flag
0: Receiver is Idle
1: Reception ongoing
Note: In Slave mode, after header reception, if DIR bit in BIDR is reset and reception starts then this
bit is set. In this case, user cannot set DTRQ bit in LINCR2.
LIN receive pin state
This bit reflects the current status of LINRX pin for diagnostic purposes.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
27-29