PXD20RM Datasheet, PDF (944/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

IRQ #
226
227
228
229
230
231
232
233
234
235
236
237
238
Offset
0x0E20
0x0E30
0x0E40
0x0E50
0x0E60
0x0E70
0x0E80
0x0E90
0x0EA0
0x0EB0
0x0EC0
0x0ED0
0x0EE0
Table 26-9. Interrupt vectors (continued)
Size
(bytes)
Resource
16
16
16
Overrun
16
16
TFFF
16
TCF
16
RFDF
16
CERR
16
16
16
16
16
IRQ_0
Reserved
Reserved
QuadSPI
Reserved
QuadSPI
QuadSPI
QuadSPI
QuadSPI
Reserved
Reserved
Reserved
Reserved
GFX2D
Module
26.6.1 Interrupt Request Sources
The INTC has two types of interrupt requests, peripheral and software configurable. These interrupt
requests can assert on any clock cycle.
26.6.1.1 Peripheral Interrupt Requests
An interrupt event in a peripheral’s hardware sets a flag bit that resides in the peripheral. The interrupt
request from the peripheral is driven by that flag bit.
The time from when the peripheral starts to drive its peripheral interrupt request to the INTC to the time
that the INTC starts to drive the interrupt request to the processor is three clocks.
External interrupts are handled by the SIU (see Section 43.6.4, External interrupts).
26.6.1.2 Software configurable Interrupt Requests
An interrupt request is triggered by software by writing a 1 to a SETx bit in
INTC_SSCIR0_3–INTC_SSCIR4_7. This write sets the corresponding flag bit, CLRx, resulting in the
interrupt request. The interrupt request is cleared by writing a 1 to the CLRx bit.
The time from the write to the SETx bit to the time that the INTC starts to drive the interrupt request to the
processor is four clocks.
26-22
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor