PXD20RM Datasheet, PDF (283/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

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hclk
m0 request
m2 request
m4 request
Park
Highest
Priority
Requester
Address/Cntrl
owner
Last Master
Master 0
Master 0 None Master 4
XBAR Master 0 XBAR
Master 4
None
Master 4 XBAR
Master 2
Master 4
Master 2
None
Master 2
XBAR
htrans
IDLE
NSEQ
IDLE
NSEQ
IDLE
NSEQ
NSEQ
IDLE
hready
Figure 9-12. Parking on last master
9.4.4.4.5 Slave Port State Machine Halt Mode
If the max_halt_request input is asserted the slave port will eventually halt all slave bus activity and go
into halt mode, which is almost identical to low power park mode. The HLP bit in the GPCR controls the
priority level of the max_halt_request in the arbitration algorithm. If the HLP bit is cleared then the
max_halt_request will have the highest priority of any master and will gain control of the slave port at
the next arbitration point (most likely the next bus cycle, unless the current master is running a locked or
fixed length burst transfer). If the HLP bit is set then the slave port will wait until no masters are actively
making requests before moving to halt mode.
Regardless of the state of the HLP bit, once the slave port has gone into halt mode as a result of
max_halt_request being asserted, it will remain in halt mode until max_halt_request is negated,
regardless of the priority level of any masters that may make requests.
In halt mode no master is selected to own the slave port so all the outputs of the slave port are set to 0.
9.5 Initialization/Application Information
No initialization is required by or for the XBAR. Hardware reset ensures all the register bits used by the
XBAR are properly initialized.
9.6 Interface
This section provides information on the XBAR interface.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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