PXD20RM Datasheet, PDF (806/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 20-20. CAN Standard Compliant Bit Time Segment Settings
Time Segment 1
5 .. 10
4 .. 11
5 .. 12
6 .. 13
7 .. 14
8 .. 15
9 .. 16
Time Segment 2
2
3
4
5
6
7
8
Resynchronization
Jump Width
1 .. 2
1 .. 3
1 .. 4
1 .. 4
1 .. 4
1 .. 4
1 .. 4
NOTE
It is the user’s responsibility to ensure the bit time settings are in compliance
with the CAN standard. For bit time calculations, use an IPT (Information
Processing Time) of 2, which is the value implemented in the FlexCAN
module.
20.5.8.5 Arbitration and Matching Timing
During normal transmission or reception of frames, the arbitration, matching, move-in and move-out
processes are executed during certain time windows inside the CAN frame, as shown in Figure 20-18.
CRC (15)
Matching/Arbitration Window (24 bits)
Start Move
(bit 6)
EOF (7)
Interm
Move
Window
Figure 20-18. Arbitration, Match and Move Time Windows
When doing matching and arbitration, FlexCAN needs to scan the whole Message Buffer memory during
the available time slot. In order to have sufficient time to do that, the following requirements must be
observed:
• A valid CAN bit timing must be programmed, as indicated in Table 20-20
• The peripheral clock frequency can not be smaller than the oscillator clock frequency, i.e. the PLL
can not be programmed to divide down the oscillator clock
• There must be a minimum ratio between the peripheral clock frequency and the CAN bit rate, as
specified in Table 20-21
20-40
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor