PXD20RM Datasheet, PDF (1328/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

39.5 External signal description
Table 39-1. SGM external interface signals
Signal
PWMO
PWMOA
SCK
DO
FS
MCLK
Description
PWM External Signals
Either PWM Block sample rate clock or composite signal
that can be filtered, amplified and fed to a buzzer or
loudspeaker (SGMCTL.OS = 1).
PWM Block pwm signal output signal.
I2S External signals
Clock out (audio data driven on this clock)
Audio serial Data Out
Frame Sync
MCLK (Auxiliary Clock) output enable
I/O Type
O logic
O logic
O logic
O logic
O logic
O logic
Voltage
Range
width
[0,VDD]
1
[0,VDD]
1
[0,VDD]
1
[0,VDD]
1
[0,VDD]
1
[0,VDD]
1
39.6 Memory map and register definition
This section describes the SGM memory map and register definition.
39.6.1 Memory map
The SGM module contains a set of control and status registers located between SGM register base +
0x0000 and 0x00FC (TBD).
Table 39-2. SGM memory map
Address
$BASE+0x0000
$BASE+0x0004
$BASE+0x0008
$BASE+0x000C
$BASE+0x0010
$BASE+0x0014
$BASE+0x0018
$BASE+0x001C
$BASE+0x0020
$BASE+0x0024
$BASE+0x0028
Register
SGMCTL
SGMCFG
CLKRSP
CLKCH3
DDSCH3
ECRACH3
ECRRCH3
ECRSCH3
NTCH3
TPCCH3
PTCCH3
Width
32
32
32
32
32
32
32
32
32
32
32
Access
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Location
on page 39-6
on page 39-8
on page 39-11
on page 39-12
on page 39-12
on page 39-13
on page 39-14
on page 39-15
on page 39-16
on page 39-16
on page 39-17
39-4
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor