PXD20RM Datasheet, PDF (454/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

PDI_PCLK
PDI[17:0]
PDI_HSYNC
PDI_DE
PDI_PCLK
PDI[17:0]
PDI_VSYNC
invalid data
1234
DELTA_X
1
invalid data
BP_H
data enable high during active data
FP_H
Data Enable in the horizontal resolution
FP_H and BP_H is programmable through register
invalid data
1234
DELTA_X
1
invalid data
PDI_DE
BP_V
FP_V
Figure 11-95. Occurrence of HSYNC and Vsync and PDI_DE for the entire frame
11.8.1.6.2 PDI input data (internal sync extraction mode)
In internal sync mode the timing parameters (horizontal and vertical blanking) are encoded into the data
stream.
Internal sync mode can only be used in 8-bit narrow mode.
In Figure 11-96, XY is used to decode the vertical and horizontal blanking period.
Table 11-79. XYh Value
Bit
Value
Description
7
1'b1 Always 1'b1. This is checked while
decoding sync preamble
6
F
Not considered in the state machine logic
5
V
1'b1 during vertical blanking
1'b0 elsewhere
4
H
1'b0 for start of active video
1'b1 for end of active video
11-120
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor