PXD20RM Datasheet, PDF (1238/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 35-25. Memory Mapped Parallel Flash Mode Address Scheme (continued)
Memory Mapped Address
32 Bit Access
0x8FFF_FFF8
0x8FFF_FFFC
Memory Mapped Address
64 Bit Access
0x8FFF_FFF8
Serial Flash A
Byte Address
0x7FF_FFFC
-
0x7FF_FFFD
0x7FF_FFFE
-
0x7FF_FFFF
Serial Flash B
Byte Address
0x7FF_FFFC
-
0x7FF_FFFD
0x7FF_FFFE
-
0x7FF_FFFF
The usable space depends from the size of the external serial flash devices. Any access beyond the size of
the external serial flash provides undefined results.
For details concerning the read process refer to Section 35.5.3.3, Flash Read.
35.4.5.5 AHB RX data buffer (QSPI_ARDB0 to QSPI_ARDB31)
The AHB RX Data Buffer register 0 to 31 can be used to read the buffer content of the RX Buffer from
successive addresses. QSPI_ARDB0 corresponds to the RX Buffer register entry corresponding to the
current value of the read pointer with increasing order.
The increment of the read pointer depends from the access scheme (DMA or flag-driven). Refer to
Section 35.5.3.3.2, Data Transfer from the QuadSPI Module Internal Buffers, topic RX Buffer, data read
via register interface and AHB read for the description of successive accesses to the RX Buffer content.
Refer also to Section 35.5.3.4, Byte Ordering of Serial Flash Read Data, for the byte ordering scheme.
Address:
0x9000_0000 for QSPI_ARDB0
0x9000_007C for QSPI_ARDB31
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
ARXD[31:16]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ARXD[15:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 35-17. AHB RX data buffer (QSPI_ARDB0 to QSPI_ARDB31)
Table 35-26. QSPI_ARDB Field Descriptions
Field
ARXD
Description
AMBA provided RX Buffer Data.
Byte order (endianess) is identical to the RX Buffer Data Registers.
35-28
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor