PXD20RM Datasheet, PDF (1243/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

35.5.3.3.2 Data Transfer from the QuadSPI Module Internal Buffers
The data read out from the external serial flash device by the QuadSPI module are stored in the internal
buffers. Depending from the buffer to which the data from the external serial flash has been loaded there
are several different ways to access these data in the internal buffers. Refer to Figure 35-1 for details about
the two available buffers, the RX Buffer and the AHB Buffer, in the QuadSPI module:
• The RX Buffer is implemented as FIFO of depth 32 entries of 4 bytes. Its content is accessible in
two different address areas both referring to the identical data.
— In the IPS address space in the area associated to QSPI_RBDR0 to QSPI_RBDR31.
— In the AHB address space in the area associated to QSPI_ARDB0 to QSPI_ARDB31. Two
successive entries are accessed with one single 64 bit AHB read operation.
RX Buffer operation can be summarized as follows: The QSPI_RBCT[WMRK] field determines
at which fill level the RXWE bit is asserted and how many entries are removed from the RX Buffer
on each Buffer POP operation. So the QSPI_SFMSR[RXWE] bit indicates that the configured
number of data entries is available in the RX Buffer and the QSPI_RBSR[RDBFL] field indicates
how many valid entries are available in total. Note that the first entry (QSPI_RBDR0 or
QSPI_ARDB0) always corresponds to the first valid entry in the RX Buffer.
Further details can be found inSection 35.4.4.15, RX Buffer Data Registers 0–31
(QSPI_RBDR0–QSPI_RBDR31), and in Section 35.4.5.5, AHB RX data buffer (QSPI_ARDB0
to QSPI_ARDB31).
• Flag-based Data Read of the RX Buffer is done by polling the QSPI_SFMFR[RXWE] bit. When
it is asserted the valid entries can be read either via the IPS address space (QSPI_RBDRn) or the
AHB address space (QSPI_ARDBn). A Buffer POP operation must be triggered by the application
by writing a 1 into the QSPI_SFMFR[RBDF] bit.
• DMA controlled Data Read of the RX Buffer is done by using the DMA capabilities of the
QuadSPI and the device containing the QuadSPI module. The application must ensure that the
DMA controller of the related device is programmed appropriately like it is described in
Section 35.6.7, DMA Usage.
DMA controlled read out is triggered fully automatically by the assertion of the
QSPI_SFMFR[RXWE] bit. The related Buffer POP operation is also handled completely inside
the QuadSPI module. Like in the case above accessing the RX Buffer content either on
QSPI_RBDRn or QSPI_ARDBn related addresses is equivalent.
• AHB Buffer data read via memory mapped access: This kind of access is done by reading one
of the addresses assigned to the external serial flash device(s) within the range given in Table 35-5
under the condition that the data requested are already present in the AHB Buffer or it is currently
read from the serial flash device. If this is not the case a memory mapped read of the AHB Buffer
is triggered like described above). As long as the requested data are already available in the AHB
Buffer they are provided to the host. The host can read the available data out of the AHB Buffer in
any order.
If the address requested by the current read is the one currently fetched by the QuadSPI module
from the serial flash the execution of the current command remains running with the AHB read
access stalled. As soon as the data from the requested address have been read by the QuadSPI
module the AHB read access is served. So it’s possible to run sequential read from the AHB buffer
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
35-33