PXD20RM Datasheet, PDF (1257/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Flash Mode, 8 cycles for Quad Mode Instructions in Individual Flash Mode, 16/32 cycles for
Dual/Single Instructions.
• Overhead due to clock domain crossing: 1 cycle
Table 35-37 below lists the number of clock cycles required to read the data from serial flash
corresponding to the different setting of the QSPI_RBCT[WMRK] field:
Table 35-37. Access Duration Examples - Serial Flash Clock Side
QSPI_RBC
T[WMRK]
Setting
# of Bytes
per DMA
Loop¹
# of SCKFx Cycles for 48 MHz Time Duration of Serial Flash Data Readout for
SCKFx
48 MHz SCKFx Frequency
IFM² IFM IFM PFM³
Single Dual Quad Quad
IFM
Single
IFM
Dual
IFM Quad
PFM
Quad
0
4
33
17
9
5
~688 ns ~354 ns ~188 ns ~104 ns
1
8
65
33
17
9 ~1.354 s ~688 ns ~354 ns ~188 ns
3
16
129 65
33
17 ~2.688 s ~1.354 s ~688 ns ~354 ns
7
32
257 129 65
33 ~5.354 s ~2.688 s ~1.354 s ~688 ns
11
48
385 193 97
49 ~8.021 s ~4.021 s ~2.021 s ~1.021 s
1 _{‘DMA Loop’ means one Minor Loop Completion which is equivalent to one Major Loop Iteration}
2 _{Individual Flash Mode}
3 _{Parallel Flash Mode}
From the examples given in Table 35-36 and Table 35-37 above it can be seen that, dependent from the
relationship between the frequencies of the bus clock and the serial flash clock, there are settings possible
where the serial flash provides the read data faster than the AHB bus can read out the RX Buffer. In the
tables above it is the case of reading the serial flash in Parallel Flash Mode with quad instructions and
QSPI_RBCT[WMRK] set to 0. In this case the RX Buffer is filled over time, to avoid the RX Buffer
overrun the IP Command used to read from flash need to specify the data size small enough.
Note also that side effects like load from other masters on the AHB bus are not considered.
35.7 Byte Ordering - Endianess
The internal byte orientation of the QuadSPI module is big endian (BE). This means that the high order
bits of the associated data vectors are associated with low order address positions.
The byte ordering is according to the following example:
35.7.1 Programming Flash Data
CPU write instructions to the QSPI_TBDR register like
(1) Write QSPI_TBDR -> 0x01_02_03_04
(2) Write QSPI_TBDR -> 0x05_06_07_08
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
35-47