PXD20RM Datasheet, PDF (652/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Register address: DMA_Offset + 0x001b
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
0
W
NOP
CEEI[0:6]
RESET:
0
0
0
0
0
0
0
= Unimplemented
Figure 16-9. DMA Clear Enable Error Interrupt (DMACEEI) Register
Table 16-9. DMA Clear Enable Error Interrupt (DMACEEI) field descriptions
Name
NOP
CEEI[0:6]
Description
No Operation
Clear Enable Error Interrupt
Value
0 Normal operation.
1 No operation, ignore bits 6-0
0-63 Clear corresponding bit in DMAEEI{H,L}
64-127 Clear all bits in DMAEEI{H,L}
16.2.1.9 DMA Clear Interrupt Request (DMACINT)
The DMACINT register provides a simple memory-mapped mechanism to clear a given bit in the
DMAINT{H,L} registers to disable the interrupt request for a given channel. The given value on a register
write causes the corresponding bit in the DMAINT{H,L} register to be cleared. A data value of 64 to 127
(regardless of the number of implemented channels) provides a global clear function, forcing the entire
contents of the DMAINT{H,L} to be zeroed, disabling all DMA interrupt requests. If bit 7 is set, the
command is ignored. This allows multiple byte registers to be written as a 32-bit word. Reads of this
register return all zeroes. See Figure 16-10 and Table 16-10 for the DMACINT definition.
Register address: DMA_Offset + 0x001c
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
0
W
NOP
CINT[0:6]
RESET:
0
0
0
0
0
0
0
= Unimplemented
Figure 16-10. DMA Clear Interrupt Request (DMACINT) Fields
Table 16-10. DMA Clear Interrupt Request (DMACINT) field descriptions
Name
NOP
CINT[0:6]
Description
No Operation
Clear Interrupt Request
Value
0 Normal operation.
1 No operation, ignore bits 6-0
0-63 Clear the corresponding bit in DMAINT{H,L}
64-127 Clear all bits in DMAINT{H,L}
16.2.1.10 DMA Clear Error (DMACERR)
The DMACEER register provides a simple memory-mapped mechanism to clear a given bit in the
DMAERR{H,L} registers to disable the error condition flag for a given channel. The given value on a
register write causes the corresponding bit in the DMAERR{H,L} register to be cleared. A data value of
64 to 127 (regardless of the number of implemented channels) provides a global clear function, forcing the
16-14
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor