PXD20RM Datasheet, PDF (620/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Offset: 0x140 (SPRIOCTR2)
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15
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CNTR[23:16]
W
Reset — 0
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CNTR[15:0]
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Reset 0
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0
= Unimplemented or Reserved
Figure 14-30. Summed Priority Counter 2 (SPRIOCTR2)
Offset: 0x144 (SPRIOCTR3)
read
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CNTR[23:16]
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Reset — 0
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CNTR[15:0]
W
Reset 0
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0
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0
0
= Unimplemented or Reserved
Figure 14-31. Summed Priority Counter 3 (SPRIOCTR3)
Offset: 0x148 (SPRIOCTR4)
read
0
1
2
3
4
5
6
7
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15
R
CNTR[23:16]
W
Reset — 0
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16
17
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31
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CNTR[15:0]
W
Reset 0
0
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0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-32. Summed Priority Counter 4 (SPRIOCTR4)
The counter registers contain 19 different 24-bit counter values. All these counter values count certain
events. XXX gives the details on the nature of the event. Counter values Summed Priority Counter 2,
Summed Priority Counter 3 and Summed Priority Counter 4 are available in 2 sets of registers. Firstly, they
are available in the registers with the same name, but they are also available in a set of 3 other registers
(granted ACK counter or cumulative wait counter registers). The multiple-mapping of the 3 upper Summed
Priority Counter registers is done to allow easy and compact DMA transfer to memory. Because of the
multiple mapping, all 19 count values can be transferred to memory with a 64-byte DMA transfer starting
14-20
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor