PXD20RM Datasheet, PDF (1480/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 43-11. PCR185–281 Field Descriptions
Field
SMC
OBE
IBE
ODE
SRC
WPE
WPS
Description
Safe Mode Control
This bit supports the overriding of the automatic deactivation of the output buffer of the associated
pad upon entering SAFE mode of the SoC.
1: In SoC SAFE mode, the output buffer remains functional.
0: In SoC SAFE mode, the output buffer of the pad is disabled.
Output Buffer Enable
This bit enables the output buffer of the pad in case the pad is in GPIO mode.
1: Output Buffer of the pad is enabled when PA = 00.
0: Output Buffer of the pad is disabled when PA = 00.
Input Buffer Enable
This bit enables the input buffer of the pad.
1: Input Buffer of the pad is enabled.
0: Input Buffer of the pad is disabled.
Open Drain Output Enable
This bit controls output driver configuration for the pads connected to this signal. Either open drain
or push/pull driver configurations can be selected. This feature applies to output pads only.
1: Open drain enable signal is asserted for the pad.
0: Open drain enable signal is negated for the pad.
Slew Rate Control
This field controls the slew rate control output signals from the SIUL. The output signals are driven
to the value of this field. The actual slew rates are defined by the implementation of the pad
devices for a given SoC.
Note: For low-power modes, keeping these bits asserted may result in more leakage. It is
recommended to not drive these bits during low-power modes.
Weak Pull Up/Down Enable
This bit controls whether the weak pull up/down devices are enabled/disabled for the pad
connected to this signal.
1: Weak pull device enabled for the pad.
0: Weak pull device disabled for the pad.
Weak Pull Up/Down Select
This bit controls whether weak pull up or weak pull down devices are used for the pads connected
to this signal when weak pull up/down devices are enabled.
1: Weak pull-up selected
0: Weak pull-down selected
It is important to configure the slew rate control correctly for the DDR pads. See Table 43-12 for
appropriate configuration values.
Table 43-12. PCR202-268 slew rate settings
SRC2
1
1
1
1
SRC1
1
1
0
0
SRC0
1
0
1
0
Mode
3.3 V SDR
1.8 V DDR2 full strength
n/a
n/a
43-14
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor