PXD20RM Datasheet, PDF (434/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

• When the cursor width is an integer multiple of 32 bits, the pixels in each row roll from one word
in the RAM to the next one. The rightmost bit in the first word in the RAM is the top leftmost pixel
on the display. The leftmost bit in the word represents a pixel that is adjacent to the rightmost bit
in the next word (in the same row). The leftmost pixel on the next row is the rightmost bit in the
first word after n words that describe the first row.
• When the cursor is greater than 32 bits but not an integer multiple of 32, the pixels in each row roll
from one word into the next one such that the rightmost bit in the first word of the row is the
leftmost bit on the display. In the final word of the row there are unused bits.
The position of the cursor on the panel is defined by register 2 in the control descriptor for the cursor
(CTRLDESCCURSOR _2). The register contains two bit fields, POSY and POSX, which determine the
location of the upper left pixel of the cursor in the x and y axes. Both fields are expressed in terms of the
number of pixels in each axis. Placing the cursor beyond the panel area is not allowed.
The cursor can be configured to blink at a particular rate when it is enabled. The EN_BLINK,
HWC_BLINK_ON, and HWC_BLINK_OFF bit fields define the blink behavior. These are in register 4
in the control descriptor for the cursor (CTRLDESCCURSOR_4). EN_BLINK enables blinking. The
blinking time is based on the frame rate, and the on and off times are independently configurable.
HWC_BLINK_ON configures the number of frame refresh cycles for which the cursor is visible.
HWC_BLINK_OFF configures the number of frame refresh cycles for which the cursor is not visible. For
a frame refresh rate of 64 Hz, the HWC_BLINK_ON and HWC_BLINK_OFF counters give a range of
on/off times up to 4 seconds.
The cursor is enabled by setting the CUR_EN bit field in register 3 in the control descriptor for the cursor
(CTRLDESCCURSOR_3).
If the DCU3 detects an invalid configuration in the cursor control descriptor, then the cursor configuration
is invalid and it cannot be made visible. In addition, the error flag HWC_ERR is set in the layer parameter
error register (PARR_ERR).
The cursor RAM may be written at any time when the TFT LCD panel is not being driven with data. This
means that the RAM can be modified when the DCU3 is not enabled and during the vertical blanking
period.
11.4.6 CLUT/tile RAM
The internal tile memory and color look up table (CLUT) memory share a common block of RAM internal
to the DCU3. Color information in this RAM is always stored as aligned 32-bit words where the
most-significant byte is the alpha component, the next byte contains the red component, the next the green
component and the least significant byte the blue component (0xAARRGGBB).
This memory block can be used to store either color look-up tables or graphics for use as a tile on a layer.
The content of the RAM at a specific address is defined by the control descriptor of a layer. The LUOFFS
bit field in the layer control descriptor defines the starting address of the area, and the BPP and TILE_EN
bit fields define what type of use the RAM area has.
11-100
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor