PXD20RM Datasheet, PDF (815/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Flash memory array blocks
Low-address space—256 K
Low-address space
8 x 16 KB + 2 x 64 KB
Mid-address space—256 K
Mid-address space
2 x 128 KB
High-address space—1.5
High-address space
2 x 256 KB
2 x 256 KB
2 x 256 KB
Figure 21-2. Flash memory segmentation
21.1.3 Features
The flash memory has these major features:
• 2MB of flash memory configured with 8 x 16KB, 2 x 64kB, 2 x 128KB and 6 x 256KB blocks.
• Support for a 64-bit data bus for instruction fetch, CPU data, DMA and Display Controller (DCU
accesses).
• Byte, halfword, word and doubleword reads are supported. Only aligned word and doubleword
writes are supported.
• Configurable read buffering and line prefetch support. Two sets of four line read buffers (128 bits
wide) and a prefetch controller are used to support single-cycle read responses for hits in the
buffers.
• Hardware and software configurable read and write access protections on a per-master basis.
• Interface to the flash array controller is pipelined with a depth of 1, allowing overlapped accesses
to proceed in parallel for interleaved or pipelined flash array designs.
• Configurable access timing allowing use in a wide range of system frequencies.
• Multiple-mapping support and mapping-based block access timing (0-31 additional cycles)
allowing use for emulation of other memory types.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
21-3