PXD20RM Datasheet, PDF (325/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

When the CONT = 1 and the CS signal for the next transfer is the same as for the current transfer, the CS
signal remains asserted for the duration of the two transfers. The delay between transfers (t_DT) is not
inserted between the transfers.
Figure 10-19 shows the timing diagram for two 4-bit transfers with CPHA = 1 and CONT = 1.
SCK
(CPOL = 0)
SCK
(CPOL = 1)
Master SOUT
Master SIN
CS
t_CSC
t_CSC = CS to SCK delay.
t_ASC = After SCK delay.
t_ASC
t_CSC
Figure 10-19. Example of Continuous Transfer (CPHA = 1, CONT = 1)
In Figure 10-19, the period length at the start of the next transfer is the sum of t_ASC and t_CSC; i.e., it does
not include a half-clock period. The default settings for these provide a total of four system clocks. In many
situations, t_ASC and t_CSC must be increased if a full half-clock period is required.
When the CONT bit = 1 and the CS signals for the next transfer are different from the present transfer, the
CS signals behave as if the CONT bit was not set.
Switching CTAR registers or changing which PCS signals are asserted between frames while using
Continuous Selection can cause errors in the transfer. The PCS signal should be negated before CTAR is
switched or different PCS signals are selected.
It is mandatory to fill the TXFIFO with the number of entries that will be concatenated together under one
PCS assertion for both master and slave before the TXFIFO becomes empty. For example, while
transmitting in master mode, it should be ensured that the last entry in the TXFIFO, after which TXFIFO
becomes empty, must have the CONT bit in the command frame as deasserted (CONT bit = 0). While
operating in slave mode, it should be ensured that when the last-entry in the TXFIFO is completely
transmitted (i.e. the corresponding TCF flag is asserted and TXFIFO is empty) the slave is de-selected for
any further serial communication; otherwise, an underflow error occurs.
10.9.5.6 Clock Polarity Switching between DSPI Transfers
If it is desired to switch polarity between non-continuous DSPI frames, the edge generated by the change
in the idle state of the clock occurs one system clock before the assertion of the chip select for the next
frame.
Refer to Section 10.8.2.3, DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn).
In Figure 10-20, time ‘A’ shows the one clock interval. Time ‘B’ is user programmable from a minimum
of two system clocks.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
10-39