PXD20RM Datasheet, PDF (748/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

18.8.2.2 Coherent Accesses
The FLAG set event can be detected by polling the FLAG bit or by enabling the interrupt or DMA request
generation.
Reading the CADR[n] again in the same period of the last read of CBDR[n] may lead to incoherent results.
This will occur if the last read of CBDR[n] occurred after a disabled B2 to B1 transfer.
18.8.2.3 Channel/Modes Initialization
The following basic steps summarize basic output mode startup, assuming the channels are initially in
GPIO mode:
1. [global] Disable Global Prescaler;
2. [timebase channel] Disable Channel Prescaler;
3. [timebase channel] Write initial value at internal counter;
4. [timebase channel] Set A/B register;
5. [timebase channel] Set channel to MC(B) Up mode;
6. [timebase channel] Set prescaler ratio;
7. [timebase channel] Enable Channel Prescaler;
8. [output channel] Disable Channel Prescaler;
9. [output channel] Set A/B register;
10. [output channel] Select timebase input through BSL[1:0] bits;
11. [output channel] Enter output mode;
12. [output channel] Set prescaler ratio (same ratio as timebase channel);
13. [output channel] Enable Channel Prescaler;
14. [global] Enable Global Prescaler.
The timebase channel and the output channel may be the same for some applications such as in
OPWFM(B) mode or whenever the output channel is intended to run the timebase itself.
At any time the flags can be configured.
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PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor