PXD20RM Datasheet, PDF (1347/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

SGM Register Base + 0x00C0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
FIFOCH3
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
FIFOCH2
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 39-20. PWM Configuration Register (PWMCR)
Table 39-23. Data FIFO Register 1
Field
Description
31-16
FIFOCH3
15-0
FIFOCH2
Data FIFO for Channel 3.
Writes to this register will be stored in the FIFO and increment the FIFO write pointer.
Data FIFO for Channel 2.
Writes to this register will be stored in the FIFO and increment the FIFO write pointer.
39.6.2.20 Data FIFO Register 2(DFIFO2)
DFIFO2 provides the Data FIFO interface for Channel 1 and Channel 0.
SGM Register Base + 0x00C4
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
FIFOCH1
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
FIFOCH0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 39-21. Data FIFO Register (DFIFO2)
Table 39-24. Data FIFO Register 2
Field
Description
31-16
FIFOCH1
15-0
FIFOCH0
Data FIFO for Channel 1.
Writes to this register will be stored in the FIFO and increment the FIFO write pointer.
Data FIFO for Channel 0.
Writes to this register will be stored in the FIFO and increment the FIFO write pointer.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
39-23