PXD20RM Datasheet, PDF (853/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

put into Low Power mode during a program or erase high voltage operation, the appropriate suspend bit
is set to a 1. The user may resume the program or erase operation at the time the module is enabled by
clearing the appropriate suspend bit. EHV must be high for the module to resume operation. If both the
ESUS and PSUS bits are set to a 1 the user must clear PSUS to resume the program. The erase may be
resumed after the program ends.
21.4.3 Power Down mode
After entering Power Down mode, the flash module turns off all DC current sources and no reads from or
writes to the module are possible. All power dissipation is due to leakage in this mode.
When in Power Down mode, register access is prevented. FC accesses are also prevented until Power
Down mode is exited.
The flash memory module returns to its pre-Power Down state when enabled in all cases unless in the
process of executing a program or erase high voltage operation at the time of entering Power Down mode.
If the flash memory module is configured to enter Power Down mode during a program or erase high
voltage operation, the appropriate suspend bit is set to a 1. The user may resume the program or erase
operation at the time the module is enabled by clearing the appropriate suspend bit. EHV must be high for
the module to resume operation. If both the ESUS and PSUS bits are set to a 1 the user must clear PSUS
to resume the program. The erase may be resumed after the program ends.
21.4.4 UTest Mode
UTest mode is a mode that customers can put the flash module in to do specific tests to check the integrity
of the Flash module.
21.4.4.1 Array Integrity Self Check
Array Integrity is checked using a pre-defined address sequence (based on UT0[AIS]), and this operation
is executed on selected and unlocked blocks. The data to be read is customer specific, thus a customer can
provide user code into the flash and the correct MISR value is calculated. The customer is free to provide
any random or non-random code, and a valid MISR signature is calculated. Once the operations is
completed, the results of the reads can be checking by reading the MISR value, to determine if an incorrect
read, or ECC detection was noted. Array integrity is controlled by the system clock (IPG), and it is required
that the Read Wait States and Address Pipelined control registers in the PFLASH2P be set to match the
user defined frequency being used. The Array Integrity Check consists of the following sequence of
events:
1. Enable UTest mode.
2. Select the block, or blocks to be receive array integrity check by writing ones to the appropriate
registers in LMS or HBS registers.
NOTE
Locked Blocks can be tested with Array Integrity if selected in LMS and
HBS.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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