PXD20RM Datasheet, PDF (1017/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

TCD (n)
RAM area
BDRL + BDRM
(4/8 bytes)
LINFlex2 regs
DMA transfer
BDRL+ BDRM
(4/8 bytes)
Frame (n)
Slave-> Master
Slave ->Slave
TCD (n+1)
Linked chain
BDRL + BDRM
(8 bytes)
TCD (n+2)
BDRL + BDRM
(4/8 bytes)
BDRL + BDRM
(8 bytes)
BDRL + BDRM
(4/8 bytes)
Extended
Frame (n+1)
Extended
Frame (n+1)
1 DMA TX channel/ filter (TCD single and/or linked chain)
Figure 27-47. TCD chain memory map (slave node, TX mode)
The TCD chain of the DMA Tx channel on a slave node supports:
• Slave to Master: transmission of the data field
• Slave to Slave: transmission of the data field
The register settings of the LINCR2, IFER, IFMR, and IFCR registers are shown in Table 27-45.
Table 27-45. Register settings (slave node, TX mode)
LIN frame
LINCR2
IFER
IFMR
IFCR
Slave to Master DDRQ = 0 To enable an ID filter
or Slave to Slave DTRQ = 0 (Tx mode) for each
HTRQ = 0 DMA TX channel
- Identifier list mode
- Identifier mask mode
DFL = payload size
ID = address
CCS = checksum
DIR = 1(TX)
The concept FSM to control the DMA Tx interface is shown in Figure 27-48. DMA TX FSM will move
to idle state if DMATXE[x] = 0, where x = IFMI – 1.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
27-61