PXD20RM Datasheet, PDF (645/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Name
ERCA
EDBG
EBW
Table 16-2. DMA Control Register (DMACR) field descriptions
Description
Value
Enable Round Robin Channel Arbitration
0 Fixed priority arbitration is used for channel
selection within each group.
1 Round robin arbitration is used for channel selection
within each group.
Enable Debug
0 The assertion of the ipg_debug input is ignored.
1 The assertion of the ipg_debug input causes the
DMA to stall the start of a new channel. Executing
channels are allowed to complete. Channel
execution will resume when either the ipg_debug
input is negated or the EDBG bit is cleared.
Enable Buffered Writes
0 The bufferable write signal (hprot[2]) is not asserted
during AMBA AHB writes.
1 The bufferable write signal (hprot[2]) is asserted on
all AMBA AHB writes except for the last write
sequence.
16.2.1.2 DMA Error Status (DMAES)
The DMAES register provides information concerning the last recorded channel error. Channel errors can
be caused by a configuration error (an illegal setting in the transfer control descriptor or an illegal priority
register setting in fixed arbitration mode) or an error termination to a bus master read or write cycle.
A configuration error is caused when the starting source or destination address, source or destination
offsets, minor loop byte count and the transfer size represent an inconsistent state. The addresses and
offsets must be aligned on 0-modulo-transfer_size boundaries, and the minor loop byte count must be a
multiple of the source and destination transfer sizes. All source reads and destination writes must be
configured to the natural boundary of the programmed transfer size respectively. In fixed arbitration mode,
a configuration error is caused by any two channel priorities being equal within a group, or any group
priority levels being equal among the groups. All channel priority levels within a group must be unique
and all group priority levels among the groups must be unique when fixed arbitration mode is enabled. If
a scatter/gather operation is enabled upon channel completion, a configuration error is reported if the
scatter/gather address (dlast_sga) is not aligned on a 32-byte boundary. If minor loop channel linking is
enabled upon channel completion, a configuration error is reported when the link is attempted if the
TCD.citer.e_link bit does not equal the TCD.biter.e_link bit. All configuration error conditions except
scatter/gather and minor loop link error are reported as the channel is activated and assert an error interrupt
request, if enabled. A scatter/gather configuration error is reported when the scatter/gather operation
begins at major loop completion when properly enabled. A minor loop channel link configuration error is
reported when the link operation is serviced at minor loop completion.
If a system bus read or write is terminated with an error, the data transfer is stopped and the appropriate
bus error flag set. In this case, the state of the channel’s transfer control descriptor is updated by the DMA
engine with the current source address, destination address and current iteration count at the point of the
fault. When a system bus error occurs, the channel is terminated after the read or write transaction which
is already pipelined after errant access, has completed. If a bus error occurs on the last read prior to
beginning the write sequence, the write will execute using the data captured during the bus error. If a bus
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
16-7