PXD20RM Datasheet, PDF (1601/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 50-1. BUCSR field descriptions
Field
Description
BBFI
Branch target buffer flash invalidate
When set, BBFI flash clears the valid bit of all BTB entries; clearing occurs regardless of the value of
the enable bit (BPEN).
Note: BBFI is always read as 0.
BALLOC
Branch Target Buffer Allocation Control
00: Branch Target Buffer allocation for all branches is enabled.
01: Branch Target Buffer allocation is disabled for backward branches.
10: Branch Target Buffer allocation is disabled for forward branches.
11: Branch Target Buffer allocation is disabled for both branch directions.
This field controls BTB allocation for branch acceleration when BPEN = 1. Note that BTB hits are not
affected by the settings of this field. Note that for branches with AA = ‘1’, the MSB of the displacement
field is still used to indicate forward/backward, even though the branch is absolute.
BPRED
Branch Prediction Control (Static)
00: Branch predicted taken on BTB miss for all branches.
01: Branch predicted taken on BTB miss only for forward branches.
10: Branch predicted taken on BTB miss only for backward branches.
11: Branch predicted not taken on BTB miss for both branch directions.
This field controls operation of static prediction mechanism on a BTB miss. Unless disabled, fetching
of the predicted target location will be performed for branch acceleration. BPRED operates
independently of BPEN, and with a BPEN setting of 0, will be used to perform static prediction of all
unresolved branches.
Note that BTB hits are not affected by the settings of this field. Note that for certain applications, setting
BPRED to a non-default value may result in improved performance.
BPEN
Branch target buffer (BTB) enable
0: BTB prediction disabled. No hits are generated from the BTB and no new entries are allocated.
Entries are not automatically invalidated when BPEN is cleared; BBFI controls entry invalidation.
1: BTB prediction enabled (enables BTB to predict branches).
Further details of the BUCSR can be found in the e200z4 core reference manual.
50.3.2 Frequency-modulated PLL0
50.3.2.1 Description
The frequency-modulated phase-locked loop (FMPLL0) allows the user to generate high speed system
clocks from a crystal oscillator or external clock generator. Further, the FMPLL0 supports programmable
frequency modulation of the system clock. This module is typically configured early in the initialization
code to ensure satisfactory performance levels are achieved.
50.3.2.2 Recommended configuration
After reset the PXD20 device uses the Fast Internal RC Oscillator (FIRC) as its system clock
(approximately 16 MHz). Typically, the source of the system clock is changed to the FMPLL0 to provide
acceptable performance. Section 8.5, Frequency-modulated phase-locked loop (FMPLL), provides details
on how the FMPLL0 should be initialized in an application. The maximum frequency of operation for this
device is specified in the device data sheet.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
50-3