PXD20RM Datasheet, PDF (740/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

write to A2
cycle n
cycle n+1
clock
prescaler
Selected
8
8
counter bus
4
1
1
A1 value
0x000004
TIME
0x000000
A2 value
0x000000
B1 value
0x000008
A1 match
A1 match posedge detection
A1 match negedge detection
match A1 negedge detection
match A1 posedge detection
B1 match
B1 match negedge detection
output pin
EDPOL = 0
FLAG set event
FLAG pin/register
match B1 negedge detection
Figure 18-31. OPWMB Mode with 0% Duty Cycle
Figure 18-32 describes the operation of the OPWMB mode with the Output Disable signal being asserted.
The Output Disable forces a transition in the output pin to the EDPOL bit value. After deasserted, the
output disable allows the output pin to transition at the following A1 or B1 match. Note that the Output
Disable does not modify the Flag bit behavior. Note that there is one system clock delay between the
assertion of the output disable signal and the transition of the output pin to EDPOL.
18-38
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor