PXD20RM Datasheet, PDF (1446/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 42-5. IRQ Register Field Description (continued)
Field
Description
6 ITGIE - Integration expired Interrupt Enable.
1 A module interrupt will occur if the ITGIF bit is set.
0 The ITGIF flag will not trigger an interrupt on the ips_int output.
0 ACOVIE - Accumulator Interrupt Enable.
1 A module interrupt will occur if the ACOVIF bit is set.
0 The ACOVIF flag will not trigger an interrupt on the ips_int output.
42.3.3.3 Integration Accumulator Register (ITGACC)
Figure 42-5 below describes the fields of the integration accumulator (ITGACC) register:
Offset 0x04
Access: User read/write
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
ITGACC
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 42-5. SSD Integration Accumulator Register (ITGACC)
The function of the ITGACC register bits is shown in Table 42-6.
Table 42-6. ITGACC Register Field Description
Field
Description
15-0
ITGACC - Integration Accumulator readout value. This 2’s complement register represents the
accumulator register of the back EMF integrator of the SSD block.
Refer to the Functional Description of the integrator for further details.
42.3.3.4 Down Counter Register (DCNT)
Figure 42-6 below describes the fields of the down counter (DCNT) register:
Offset 0x06
Access: User read/write
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
DCNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 42-6. SSD Down Counter Register (DCNT)
The function of the DCNT register bits is shown in Table 42-7.
42-8
PXD20 Microcontroller Reference Manual, Rev. 1